Problem

Reboots after POST.

Diagnosis

Another Gradius III on the table…

Probing CPU 1 with a logic analyzer showed program execution spinning in a loop waiting for shared RAM location 0x003956 to change, before the CPU is eventually reset by the watchdog circuit:

Shortly before entering the loop, CPU 1 is meant to trigger a level 4 interrupt on CPU 2 by writing to 0xd8000. We can check if this is actually happening by setting the logic analyzer to trigger around an access to 0xd8000:

The CPU1->CPU2 interrupt generation logic appeared to be broken. I traced the source of /IPL2 back to a 74LS174 at R2, which looked very corroded:

One fresh 74LS174 later and we were back to partying like it was 1989 while failing to get beyond stage one…

Fix

Replace 74LS174 at R2.

Philip Bennett